This invention relates, in general, to package lead bond inspection for semiconductor chips, and more particularly to bond inspection techniques which can evaluate all bonds on a semiconductor chip simultaneously.
Pin counts for semiconductor chips are increasing at a fantastic rate. New package techniques are emerging to handle pin counts ranging from 256 pins to over several thousand pins. Package interconnects or package leads which contact a semiconductor chip must be extremely small and tightly spaced to accommodate these large numbers. Package leads are bonded to a contact pad on the semiconductor chip to insure electrical connection from the semiconductor chip to the package lead. Knowledge of the integrity of each bond on a semiconductor chip is essential to cull out bad parts and to eliminate parts which may have package lead bonds that may fail or cause intermittent problems over the lifetime of the semiconductor chip due to vibration or some other failure mechanism.
Current test strategies for evaluating bonds do not adequately meet quality, test throughput, and long term reliability issues involved with high pin count semiconductor chips. Tests commonly used include visual inspection, electric continuity, and destructive tests. For example, a TAB package may have several hundred package leads connected to a semiconductor chip. The package leads are very small and tightly spaced. A visual inspection may turn up only gross defects in the bonding process and will not determine the electrical characteristics of each package lead to semiconductor chip bond. An electric continuity test proves a connection exists between a package lead and the semiconductor chip but may not show high current problems with the connection or long term problems which could develop due to a poor bond. Long term testing under high current or high stress conditions is a solution to this problem but is very costly. A destructive test is a test through sampling. The quality of a package lead bond can be determined by physically pulling a package lead from the semiconductor device. The higher the force needed to pull a package lead from a semiconductor chip the stronger the bond. This test destroys the bond which is tested, thus it is a destructive test, the results of the destructive test are used to infer whether other bonds on the semiconductor chip are good. The destructive test assumes other bonds on the semiconductor chip are formed similarly to the bond destroyed in the test. A random sampling using the destructive test will not adequately determine the integrity of all bonds on the semiconductor chip as pin counts increase and package lead spacings are made smaller. Even using all three of these tests may not meet quality standards set up by semiconductor chip manufacturers.
It would be of great benefit if a technique for testing a high pin count semiconductor chip can be developed which rapidly evaluates all package lead to semiconductor chip bonds, determines bond current handling capability, and is easily automated with existing equipment.